Although TSMC can’t claim to be the first fab to use extreme UV (EUV) lithography – that title goes to Samsung – they do get to claim to be the largest. As a result, the company has developed significant experience with EUV over the years, allowing TSMC to refine how they use EUV tooling to both improve productivity/uptime, and to cut down on the costs of using the ultra-fine tools. As part of the company’s European Technology Symposium this week, they went into a bit more detail on their EUV usage history, and their progress on further integrating EUV into future process nodes.
When TSMC started making chips using EUV lithography in 2019 on its N7+ process (for Huawei’s HiSilicon), it held 42% of the world’s installed base of EUV tools, and even as ASML ramped up shipments of EUV scanners in 2020, TSMC’s share of EUV installations actually increased to 50%. And jumping ahead to 2024, where the number of EUV litho systems at TSMC has increased by 10-fold from 2019, TSMC is now 56% of the global EUV installed base, despite Samsung and Intel ramping up their own EUV production. Suffice it to say, TSMC made a decision to go in hard on EUV early on, and as a result they still have the lion’s share of EUV scanners today.
Notably, TSMC’s EUV wafer production has increased by an even larger factor; TSMC now pumps out 30 times as many EUV wafers as they did in 2019. Compared to the mere 10x increase in tools, TSMC’s 30x jump in production underscores how TSMC has been able to increase their EUV productivity, reduce service times, and fewer tool downtimes overall. Apparently, this has all been accomplished using the company’s in-house developed innovations.
| TSMC’s Leadership in EUV High Volume Manufacturing Data by TSMC (Compiled by AnandTech) | ||
| 2019 | 2023 | |
| Cumulative Tools | 1X | 10X |
| Share of Global EUV Installed Base | 42% | 56% |
| EUV Wafer Output | 1X | 30X |
| Wafer per Day per EUV Tool | 1X | 2X |
| Reticle Particle Contamination | 1X | 0.1X |
TSMC says that it has managed to increase wafer-per-day-per-tool productivity of its EUV systems by two times since 2019. To do so, the company optimized the EUV exposure dose and the photoresist it uses. In addition, TSMC greatly refined its pellicles for EUV reticles, which increased their lifespan by four times (i.e., increases uptime), increased output per pellicle by 4.5 times, and lowered defectivity by massive 80 times (i.e., improves productivity and increases uptime). For obvious reasons, TSMC does not disclose how it managed to improve its pellicle technology so significantly, but perhaps over time the company’s engineers are going to share this with academia.
| TSMC’s EUV Pellicle Technology vs. Commercial Data by TSMC (Compiled by AnandTech) | ||
| Commercial | TSMC (Claimed) | |
| Output | 1X | 4.5X |
| Defectivity | 1X | 0.0125X |
| Lifespan | 1X | 4X |
EUV lithography systems are also notorious for their power consumption. So, in addition to improving productivity of EUV tools, the company also managed to reduce the power consumption of its EUV scanners by 24% through undisclosed ‘innovative energy saving techniques.’ And the company isn’t done there: they are planning to improve energy efficiency per wafer per EUV tool by 1.5 times by 2030.
Considering all the refinements that TSMC has managed to achieve with Low-NA EUV lithography by now, it is not terribly surprising that the company is quite confident that it can continue to produce cutting-edge chips in the future. Whereas rival Intel has gone all-in on High-NA EUV for their future, sub-18A nodes, TSMC is looking to leverage their highly-optimized and time-tested Low-NA EUV tooling instead, avoiding the potential pitfalls of a major technology transition so soon while also reaping the cost benefits of using the well-established tooling.
