Designing chips for modern, leading-edge manufacturing technologies is an expensive endeavor. Still, dozens of companies have already adopted TSMCs N3 and N3E (3 nm-class) fabrication processes, according to disclosures made by TSMC and Synopsys.
“Synopsys IP for TSMC’s 3nm process has been adopted by dozens of leading companies to accelerate their development time, quickly achieve silicon success and speed their time to market,” said John Koeter, senior vice president of marketing and strategy for IP at Synopsys.
TSMC has been producing chips using its latest N3 (aka N3B) fabrication technology (with up to 25 EUV layers and support for EUV double patterning) since late 2022 and intends to start making products on its simplified N3E manufacturing process (with up to 19 EUV layers and without EUV double patterning) in Q4 2023.
Previously, TSMC disclosed that its N3 nodes had been adopted by designers of high-performance computing (HPC) and smartphone SoCs and that the number of adopters was higher compared to N5 early in its lifecycle. Meanwhile, TSMC never mentioned the number of companies that had decided to use its 3 nm-class fabrication processes.
Synopsys is a major IP developer and electronic design automation tools provider, so it means a lot when it says that dozens of companies have licensed its IP for TSMC’s N3 fabrication technologies. But Synopsys is not the only IP designer out there, and companies like Cadence also supplied their N3-compatible IP to other fabless chip developers. It is safe to say that the number of their clients is also significant.
TSMC’s N3 family of process technologies includes baseline N3 (N3B), relaxed N3E with a bit reduced transistor density but widened process window for better yields, performance-enhanced N3P that is IP compatible with N3E will be production ready in the second half of 2024, and N3X for extremely high-performance applications that are due in 2025.
The IP licensed by Synopsys right now can be used for N3, N3E, and N3P production nodes.
Sources: Synopsys
